Senior Staff System IP Design Verification

... Description: Title: Senior System IP Design Verification Engineer (Contract) ... a Senior Staff System IP Design Verification Engineer to lead verification efforts for advanced System IP (coherent ... reusable testbenches and verification environments from scratch ...

Description: Job Title: System IP Design Verification Engineer Duration: 6 Months Location: Austin, TX, USA / San Jose, CA (Hybrid) Note: GLS verification experience, preferably on SoC designs." Good hands-on experience in debugging GLS. Must Have: ...

Description: We are looking for Design Verification Engineer for our client in Austin, TX Job Title: Design Verification Engineer Job Location: Austin, TX Job Type: Contract Job Description: Responsibilities: Work closely with design and architecture ...

Description: Job role: DV Must have good knowledge on the verification flows Experience in debug skills and problem-solving attitude. Complex test-bench/model in Verilog, System Verilog or SystemC Working on Functional Verification, SoC Verification, ...