Description:
Job role: DV Must have good knowledge on the verification flows Experience in debug skills and problem-solving attitude. Complex test-bench/model in Verilog, System Verilog or SystemC Working on Functional Verification, SoC Verification, Emulation Good in programming: System Verilog, PLI/DPI interface, C/C++, PERL/Shell script, assembly language OVM/UVM Methodology knowledge and experience Must have good communication skills and the ability to work in a team environment. Preferably havin
Apr 4, 2025;
from:
dice.com