Description:
Job Title: System IP Design Verification Engineer Duration: 6 Months Location: Austin, TX, USA / San Jose, CA (Hybrid) Note: GLS verification experience, preferably on SoC designs." Good hands-on experience in debugging GLS. Must Have: Minimum 10 years of experience in verification of DV role along withHands on UVM, system Verilog and TestbenchGate Level simulation Primary skillsRTL designMajority of work will be on Gate level simulationThis will be a ands on roleNice to have: LPDDR memoryco
Apr 18, 2025;
from:
dice.com