Description:
Job Title: Verification Lead UVM / System Verilog / RTL Verification Location: 100% Onsite Austin, TX 12+ Months Contract Top Must-Have Skills: UVM System Verilog RTL Verification Role Overview: We are seeking a seasoned Verification Lead with expertise or strong interest in IO/PHY verification. The ideal candidate will have a proven track record in IP verification, UVM, and SystemVerilog, with the ability to lead Design Verification (DV) teams and collaborate with world-class design and engi
Nov 11, 2025;
from:
dice.com