Description:
Design Verification Engineer 100% Onsite Role in Austin, TX TOP MUST HAVE SKILLS: UVM, SystemVerilog, RTL verification THE ROLE: We are seeking a seasoned verification lead with expertise or significant interest in IO/PHY verification. You have had significant success drivingIP verification, UVM and SystemVerilog. This senior role will stretch you as you lead DV teams in new directions, network with our world-class design/DV teams. THE PERSON: You have excellent communication and presentati
Nov 4, 2025;
from:
dice.com