... Senior System IP Design Verification Engineer (Contract)Duration: Through 09/12 ... Staff System IP Design Verification Engineer to lead verification efforts ... UVM, SystemVerilog, and gate-level simulation (GLS). Key ResponsibilitiesDevelop reusable testbenches ...
5 days ago
... Title: System IP Design Verification Engineer Duration: 6 Months Location: Austin, TX ... , system Verilog and TestbenchGate Level simulation Primary skillsRTL designMajority of work ...
11 days ago