... : Senior System IP Design Verification Engineer (Contract)Duration: Through 09/12 ... Staff System IP Design Verification Engineer to lead verification efforts for ... , caches). This is a hands-on role requiring deep experience in UVM ...
14 days ago
... Title: System IP Design Verification Engineer Duration: 6 Months Location: Austin, TX ... experience in verification of DV role along withHands on UVM, system ...
20 days ago