Description: Role: Senior Software Engineer Location: Austin, TX Duration: 6+ Months ... , including expertise in databases, large data processing, networking, and performance optimization ...
7 days ago
... : Senior System IP Design Verification Engineer (Contract)Duration: Through 09/12 ... Staff System IP Design Verification Engineer to lead verification efforts for ... in UVM, SystemVerilog, and gate-level simulation (GLS). Key ResponsibilitiesDevelop reusable ...
4 days ago
... Title: System IP Design Verification Engineer Duration: 6 Months Location: Austin, TX ... UVM, system Verilog and TestbenchGate Level simulation Primary skillsRTL designMajority of ... work will be on Gate level simulationThis will be a ands on ...
10 days ago