Description:
Minimum Qualifications: UVM with SVM, System Verilog, CPU AMBA protocols AXI with addition one or more protocols like i3c, SPI, OCP etc Design Verification Engineering Services Testbench development System Verilog Universal Methodology ( UVM ), Python, and C tests Integration/development of C tests/Application Programming Interface ( APIs ) and software build flow Integration of UVM testbenches Test development and debug, including without limitation tests for functionality, power, performance,
Sep 8, 2025;
from:
dice.com