Description:
Role: Design Verification EngineerLocation: Sunnyvale, CA or Austin, Texas Role PurposeKey Responsibilities:Strong understanding of SV, UVM, and debugging skills.Knowledge of AMBA protocols.Develop test plans based on functional and architectural requirements.Build UVM/System Verilog verification environments for IP/SoC testing.Create directed and random test cases, perform coverage analysis.Debug simulation failures with RTL designers.Execute regression runs, analyze results, and improve proce
Aug 13, 2025;
from:
dice.com