Description: Job role: DV Must have good knowledge on the verification flows Experience in debug skills and problem-solving attitude. Complex test-bench/model in Verilog, System Verilog or SystemC Working on Functional Verification, SoC Verification, ...
20 days ago
... user permissions to ensure data security both externally and between user ...
30 days ago
... and mentor a team of QA engineers. Collaborate with stakeholders to align ...
27 days ago