Description:
Design for Test Engineer (DFT) The role is Design for Test (DFT) for high-performance designs going into industry AI/ML architectures. This will be involved in all implementation aspects from RTL to tapeout for various IPs on the chip. High level challenges include reducing test cost while attaining high coverage & facilitating debug and yield learnings while minimizing design intrusions. Scope: Implementation of DFT features into RTL (using Verilog). Understand DFT Architectures & micro-archit
Apr 14, 2025;
from:
dice.com